1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device, and in particular to a structure which determines states of externally applied control signals to identify a designated internal operation.
2. Description of the Background Art
In accordance with increase of an operation speed of CPUs (Central Processing Units), i.e., external processing units, it has been demanded to increase an operation speed of DRAMs (Dynamic Random Access Memories) used as system memories of main storage units. As a memory satisfying the above demand for the high speed operation, there has been a synchronous semiconductor memory device which operates in synchronization with an external clock signal such as a system clock. The synchronous semiconductor memory device (which will also be referred to as an SDRAM (Synchronous Dynamic Random Access Memory) determines the states of external signals, e.g., at the time of rising of an external clock signal, decides the internal operation to be executed in accordance with the result of determination, and executes the decided internal operation. Since the states of external control signals are determined at the time of rising of the external clock signal (which will be referred to as a clock signal), it is not necessary to take into consideration a margin with respect to skew of the external control signals, for example, so that the internal operation can be started at an earlier timing, and therefore high-speed access can be achieved. Since input/output of data are performed in synchronization with the clock signal, the input/output of data can be performed rapidly.
In the above SDRAM, the external control signals are in a pulse form. Since the external control signals have the same pulse form as the clock signal, it is only necessary to generate the external control signals in synchronization with the clock signal, so that control by the external control device can be made easy. Since the skew of the external control signal is the same as that of the clock signal, it is not necessary to take into consideration a margin for a set-up time and a hold time of the external control signal with respect to the clock signal, so that an internal operation can be started faster. In SDRAM including banks which operate independently from each other, the external control signals in the pulse form allow activation of one of the banks while another bank is active. Therefore, the banks can be alternately activated and accessed. This results in that an RAS precharge period (period required from deactivation of a row address strobe signal ZRAS to subsequent activation) which is required in a standard DRAM is hidden from the external, so that input/output of data can be performed at high speed.
FIG. 11 shows a relationship between designated internal operations and states of the external control signals in the SDRAM.
Since designation of the internal operation mode is made with a plurality of external control signals, a set of states of the external control signals will be referred to as a "command".
The external control signals to be used are specifically a row address strobe signal extZRAS, an external column address strobe signal extZCAS and an external write enable signal extZWE.
[NOP Command]
In FIG. 11, if all of external control signals extZRAS, extZCAS and extZWE are held at H-level when an externally applied clock signal extCLK rises at time T0, an internal operation is not designated. The state of the last cycle is maintained in the SDRAM.
[Read Command]
When clock signal extCLK rises at time T1 in FIG. 11, both control signals extZRAS and extZWE are set to H-level, and column address strobe signal extZCAS is set to L-level. This combination of the states of external control signals is called a read command, which designates output (read) of data in the SDRAM. When this read command is received, an internal column address strobe signal CAS0, which activates the column selection operation in the SDRAM, is activated. This signal CAS0 is in the one-shot pulse form, and is used as a trigger signal. In order to activate the data reading, a read trigger (read instruction) signal ZR is set active for a predetermined period.
[Write Command]
When clock signal extCLK rises at time T2 in FIG. 11, external row address strobe signal extZRAS is set to H-level, and both external control signals extZCAS and extZWE are set to L-level. This state is called a write command, which designates the writing of data into the SDRAM. When the write command is received, internal column address strobe signal CAS0, which functions as a trigger signal for activating the column select operation in the SDRAM, is activated. Also, internal write enable signal WE0 designating the internal data writing is activated. In response to internal write enable signal WE0, a write instruction signal ZW for triggering the writing of data into the SDRAM is activated.
[Precharge Command]
When clock signal extCLK rises at time T3 in FIG. 11, both external control signals extZRAS and extZWE are set to L-level, and column address strobe signal extZCAS is set to H-level. This state is called a precharge command, by which an operation is performed to set internally the SDRAM to a precharge state (standby state). When the precharge command is applied, internal row address strobe signal RAS0 and internal write enable signal WE0 are set active for a predetermined period, and a precharge trigger signal ZPC for triggering the precharge operation is set active for a predetermined period.
[Active Command]
When clock signal extCLK rises at time T4 in FIG. 11, row address strobe signal extZRAS is set to L-level, and both external control signals extZCAS and extZWE are set to H-level. This state is called an active command, by which a memory cell selection operation in the SDRAM is activated. When this active command is received, internal row address strobe signal RAS0 is activated, and thereby an active trigger (instruction of start of internal operation) signal ZA for activating the memory cell selection operation is set active for a predetermined period.
FIG. 12 schematically shows a structure of an external control signal input selection. In FIG. 12, there are arranged a RAS input buffer 1a, a CAS input buffer 1b and a WE input buffer 1c, which correspond to external control signals extZRAS, extZCAS and extZWE and produce one shot internal control signals RAS0, CAS0 and WE0 in synchronization with clock signal CLK, respectively. These input buffers 1a, 1b and 1c set the related internal control signals to H-level for a predetermined period when the corresponding external control signals are at L-level at the time of rising of clock signal CLK.
There are arranged inverters 3a-3c corresponding to input buffers 1a-1c for producing inverted signals ZRAS0, ZCAS0 and ZWE0 of internal control signals RAS0, CAS0 and WE0, respectively. Internal control signals RAS0, CAS0 and WE0 from input buffers la-ic as well as the inverted signals of these internal control signals are applied to a command decoder 4.
Command decoder 4 sets trigger signals ZA, ZR, ZW and ZPC to the active state for a predetermined period to activate a required internal operation in accordance with combination of states of the applied internal control signals.
FIG. 13A schematically shows a structure of input buffer 1 (1a-1c) shown in FIG. 12. Input buffers 1a-1c have the same structure. In FIG. 13A, the external control signal is indicated by reference characters EXT, and the external control signal is indicated by reference characters INT.
In FIG. 13A, input buffer 1 (1a-1c) includes an inverter 5 receiving external control signal EXT, an NAND circuit 6 receiving the output signal of inverter 5 and clock signal CLK, and a pulse generator 7 which generates a pulse in response to falling of the output signal of NAND circuit 6. Pulse generator 7 generates internal control signal INT in a pulse form which attains H-level for a predetermined period. Operation of the input buffer shown in FIG. 13A will be described below with reference to a waveform diagram of FIG. 13B.
When clock signal CLK is at L-level, the output signal of NAND circuit 6 is fixed at H-level. When external control signal EXT is at H-level, the output signal of inverter 5 is at L-level, and the output signal of NAND circuit 6 is held at H-level. In this state, pulse generator 7 generates no pulse, and internal control signal INT is maintained at the inactive state of L-level.
If external control signal EXT is at L-level when clock signal CLK rises, the output signal of NAND circuit 6 falls to L-level in response to this rising of clock signal CLK. In response to falling of the output signal of NAND circuit 6, pulse generator 7 holds internal control signal INT at H-level for a predetermined period. Deactivation of internal control signal INT generated from pulse generator 7 may be done in accordance with a timing which is determined in advance in pulse generator 7, or may be done in synchronization with falling of clock signal CLK.
FIG. 14 schematically shows a structure of command decoder 4 shown in FIG. 12. As shown in FIG. 14, command decoder 4 is formed of NAND-type decoder circuits which are provided corresponding to the internal trigger signals. More specifically, active operation trigger signal ZA is generated from an NAND circuit 4a receiving internal control signals RAS0, ZCAS0 and ZWE0. Read operation trigger signal ZR is generated from an NAND circuit 4b receiving internal control signals ZRAS0, CAS0 and ZWE0. Write operation trigger signal ZW is generated from an NAND circuit 4c receiving internal control signals ZRAS0, CAS0 and WE0. Precharge operation trigger signal ZPC is generated from an NAND circuit 4d receiving internal control signals RAS0, ZCAS0 and WE0.
In accordance with these trigger signals from the command decoder, a control circuit (not shown) operates to execute a designated internal operation.
Owing to the structures of input buffers and command decoder described above, the trigger signal for an internal operation is output in synchronization with clock signal CLK for starting the internal operation. As shown in FIG. 14, however, the trigger signals for the respective operation modes are generated from NAND circuits 4a-4d which are arranged in parallel with each other. NAND circuits 4a-4d each generate the corresponding trigger signal in accordance with the states of applied internal control signals regardless of the states of the other trigger signals.
In the SDRAM, when the active command is supplied, the internal precharge state (standby state) is released, and the memory cell selection operation starts. In order to read or write data of memory cells, therefore, it is necessary to supply the commands in the order of (1) active command, (2) read command or write command, and (3) precharge command.
Therefore, even when the read command, write command or precharge command is supplied, the SDRAM does not accurately perform the designated internal operation unless the active command is supplied. When the active command is not supplied, selection of memory cells is not performed, so that a selected memory cell does not exist, and therefore the normal data reading cannot be performed even if the read command is applied. In this case, the I/O circuit is enabled by the trigger signal produced in accordance with the read command or write command.
Usually, the write, read or precharge command is not supplied without supplying the active command. However, in the case of an erroneous sequence (supply of a command other than the active command prior to supply of the active command), a signal triggering an operation corresponding to the supplied command is activated in accordance with the supplied command even if the active command is inactive, as shown in FIG. 13A and FIG. 14. Therefore, circuits operate unnecessarily, resulting in increase of power consumption. Also, internal circuits of the SDRAM may malfunction in accordance with the erroneously activated trigger signal.